525 Almanor Ave
Sunnyvale, CA 94085
Centers around the efficiency and scalability of next-generation micro-processors for the emerging planet-scale applications. With domain specific architecture and kilo-scale networks, I believe the future heterogeneous manycore micorprocessor would provide unprecedented computation power and efficiency, empowering us to better acquire, process and understand the information of the world.
I have spent my last 10 years in pursuing this goal, taped out multiple novel microprocessor along with the toolchains/runtime support, including the MaPU architecture with Ultra VLIW (14 slots) and CGRA feature, and Celerity, a 511 RISC-V core chip with record-breaking benchmark scores.
Recently, I’m interested in open source processor architecture (RISC-V), and hardware/software stack of Domain Specific Accelerator (DSP, Deep Learning, Data Center, IoT).
|Nov 29, 2017||Joining University of Washington as a research scientiest.|
|Jul 2, 2017||Celerity: An Open Source RISC-V Tiered Accelerator Fabric published at Hotchip’17, California, United States.|
|May 2, 2017||Taped out the 511 RISC-V cores chip with bleeding edge TSMC 16nm nodes!|
|Jul 2, 2016||Joining University of California, San Diego as visiting scholar/research staff|
|Mar 23, 2016||MaPU: A novel mathematical computing architecture published, and gave talk at HPCA’16, Barcelona, Spain.|