Celerity is an accelerator-centric system-on-chip (SoC) which uses a tiered accelerator fabric to improve energy efficiency in the context of high-performance embedded systems.

The SoC is a 5x5 mm2 385 M-transistor chip in TSMC 16 nm designed and implemented by a modest team of over 20 students and faculty from the University of Michigan, Cornell University, and the Bespoke Silicon Group (now at U. Washington) as part of the DARPA Circuit Realization At Faster Timescales (CRAFT) program.

Celerity currently holds the world record for RISC-V performance; 500B RISC-V instructions per second, beating prior records by 100X.

SoC Structure

General Purpose Tier

A few fully featured RISC-V processors capable of running general-purpose software including an operating system. Modified version of Berkeley Rocket core.

Massive Parallel Tier

A manycore comprising hundreds of lightweight RISC-V processors, a distributed shared memory system, and a mesh-based interconnect.

Specialization Tier

Application-specific accelerators (possibly generated using high-level synthesis).

Publication

Please cite following paper if you find our research helpful:

@article{davidson2018celerity,
 title={The Celerity open-source 511-core RISC-V tiered accelerator fabric: Fast architectures and design methodologies for fast chips},
 author={Davidson, Scott and Xie, Shaolin and Torng, Christopher and Al-Hawai, Khalid and Rovinski, Austin and Ajayi, Tutu and Vega, Luis and Zhao, Chun and Zhao, Ritchie and Dai, Steve and others},
 journal={IEEE Micro},
 volume={38},
 number={2},
 pages={30--41},
 year={2018},
 publisher={IEEE}
 }
  1. A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor With Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS Rovinski, Austin, Zhao, Chun, Al-Hawaj, Khalid, Gao, Paul, Xie, Shaolin, Torng, Christopher, Davidson, Scott, Amarnath, Aporva, Vega, Luis, Veluri, Bandhav, Rao, Anuj, Ajayi, Tutu, Puscar, Julian, Dai, Steve, Zhao, Ritchie, Richmond, Dustin, Zhang, Zhiru, Galton, Ian, Batten, Christopher, Taylor, Michael B, and Dreslinski, Ronald G In 2019 Symposium on VLSI Circuits 2019
  1. Evaluating Celerity: A 16-nm 695 Giga-RISC-V Instructions/s Manycore Processor With Synthesizable PLL Rovinski, Austin, Zhao, Chun, Al-Hawaj, Khalid, Gao, Paul, Xie, Shaolin, Torng, Christopher, Davidson, Scott, Amarnath, Aporva, Vega, Luis, Veluri, Bandhav, Rao, Anuj, Ajayi, Tutu, Puscar, Julian, Dai, Steve, Zhao, Ritchie, Richmond, Dustin, Zhang, Zhiru, Galton, Ian, Batten, Christopher, Taylor, Michael B., and Dreslinski, Ronald G. IEEE Solid-State Circuits Letters 2019
  1. The Celerity open-source 511-core RISC-V tiered accelerator fabric: Fast architectures and design methodologies for fast chips Davidson, Scott, Xie, Shaolin, Torng, Christopher, Al-Hawai, Khalid, Rovinski, Austin, Ajayi, Tutu, Vega, Luis, Zhao, Chun, Zhao, Ritchie, Dai, Steve, and others, IEEE Micro 2018
  1. Celerity: An open source RISC-V tiered accelerator fabric Ajayi, Tutu, Al-Hawaj, Khalid, Amarnath, Aporva, Dai, Steve, Davidson, Scott, Gao, Paul, Liu, Gai, Lotfi, Atieh, Puscar, Julian, Rao, Anuj, and others, In Hot Chips: A Symposium on High Performance Chips 2017
  1. The BaseJump Manycore Accelerator Network Xie, Shaolin, and Taylor, Michael Bedford arXiv preprint arXiv:1808.00650 2018
  1. Experiences Using the RISC-V Ecosystem to Design an Accelerator-Centric SoC in TSMC 16nm Ajayi, Tutu, Al-Hawaj, Khalid, Amarnath, Aporva, Dai, Steve, Davidson, Scott, Gao, Paul, Liu, Atieh, Puscar, Julian, Rao, Anuj, and others, 2017