Publications

Publications by categories in reversed chronological order. Generated by jekyll-scholar.

2024

  1. Scalable, Programmable and Dense: The HammerBlade Open-Source RISC-V Manycore
    Dai Cheol Jung, Max Ruttenberg, Paul Gao, and 8 more authors
    In 2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture (ISCA), 2024

2020

  1. A 7.3 M Output Non-Zeros/J, 11.7 M Output Non-Zeros/GB Reconfigurable Sparse Matrix–Matrix Multiplication Accelerator
    Dong-Hyeon Park, Subhankar Pal, Siying Feng, and 15 more authors
    IEEE Journal of Solid-State Circuits, 2020
    DOI

2019

  1. Evaluating Celerity: A 16-nm 695 Giga-RISC-V Instructions/s Manycore Processor With Synthesizable PLL
    Austin Rovinski, Chun Zhao, Khalid Al-Hawaj, and 18 more authors
    IEEE Solid-State Circuits Letters, 2019
    DOI
  2. A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor With Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS
    Austin Rovinski, Chun Zhao, Khalid Al-Hawaj, and 18 more authors
    In 2019 Symposium on VLSI Circuits, 2019
    DOI
  3. A 7.3 M Output Non-Zeros/J Sparse Matrix-Matrix Multiplication Accelerator using Memory Reconfiguration in 40 nm
    Subhankar Pal, Dong-hyeon Park, Siying Feng, and 15 more authors
    In 2019 Symposium on VLSI Technology, 2019
    DOI

2018

  1. The Celerity open-source 511-core RISC-V tiered accelerator fabric: Fast architectures and design methodologies for fast chips
    Scott Davidson, Shaolin Xie, Christopher Torng, and 8 more authors
    IEEE Micro, 2018
  2. Fast and efficient deep sparse multi-strength spiking neural networks with dynamic pruning
    Ruizhi Chen, Hong Ma, Shaolin Xie, and 3 more authors
    In 2018 International Joint Conference on Neural Networks (IJCNN), 2018
  3. FBNA: A Fully Binarized Neural Network Accelerator
    Peng Guo, Hong Ma, Ruizhi Chen, and 3 more authors
    In 2018 28th International Conference on Field Programmable Logic and Applications (FPL), 2018
  4. The BaseJump Manycore Accelerator Network
    Shaolin Xie, and Michael Bedford Taylor
    arXiv preprint arXiv:1808.00650, 2018
  5. Low Latency Spiking ConvNets with Restricted Output Training and False Spike Inhibition
    Ruizhi Chen, Hong Ma, Peng Guo, and 3 more authors
    In 2018 International Joint Conference on Neural Networks (IJCNN), 2018
  6. Extreme Datacenter Specialization for Planet-Scale Computing: ASIC Clouds
    Shaolin Xie, Davidson Scott, Magaki Ikuo, and 4 more authors
    ACM SIGOPS Operating Systems Review, 2018
  7. Parallel Polar Encoding in 5G Communication
    Yang Guo, Shaolin Xie, Zijun Liu, and 2 more authors
    In 2018 IEEE Symposium on Computers and Communications (ISCC), 2018
  8. Parallel filtering method and corresponding apparatus
    Donglin Wang, Leizu Yin, Yongyong Yang, and 2 more authors
    May 2018
    US Patent 9,966,932
  9. Progress in a novel architecture for high performance processing
    Zhiwei Zhang, Meng Liu, Zijun Liu, and 8 more authors
    Japanese Journal of Applied Physics, May 2018

2017

  1. Celerity: An open source RISC-V tiered accelerator fabric
    Tutu Ajayi, Khalid Al-Hawaj, Aporva Amarnath, and 8 more authors
    In Hot Chips: A Symposium on High Performance Chips, May 2017
  2. Experiences Using the RISC-V Ecosystem to Design an Accelerator-Centric SoC in TSMC 16nm
    Tutu Ajayi, Khalid Al-Hawaj, Aporva Amarnath, and 7 more authors
    May 2017
  3. A self-indexed register file for efficient arithmetical computing hardware
    Lei Yang, Shaolin Xie, Zijun Liu, and 2 more authors
    In 2017 9th Computer Science and Electronic Engineering (CEEC), May 2017
  4. A reconfigurable ASIC-like image polyphase interpolation implementation method
    Lei Yang, Ruoshan Guo, Shaolin Xie, and 1 more author
    In 2017 7th IEEE International Conference on Electronics Information and Emergency Communication (ICEIEC), May 2017

2016

  1. MaPU: A novel mathematical computing architecture
    Donglin Wang, Shaolin Xie, and  others
    In 2016 IEEE International Symposium on High Performance Computer Architecture (HPCA), May 2016
  2. Methods and devices for multi-granularity parallel FFT butterfly computation
    Donglin Wang, Tao Wang, Shaolin Xie, and 2 more authors
    Feb 2016
    US Patent 9,262,378
  3. Data access method and device for parallel FFT computation
    Shaolin Xie, Donglin Wang, Xiao Lin, and 4 more authors
    Apr 2016
    US Patent 9,317,481
  4. Parallel bit reversal devices and methods
    Shaolin Xie, Donglin Wang, Jie Hao, and 2 more authors
    Feb 2016
    US Patent 9,268,744

2015

  1. Multi-granularity parallel storage system
    Donglin Wang, Zijun Liu, Xiaojun Xue, and 3 more authors
    Oct 2015
    US Patent 9,171,593
  2. Multi-granularity parallel storage system and storage
    Donglin Wang, Shaolin Xie, Xiaojun Xue, and 2 more authors
    Sep 2015
    US Patent 9,146,696