Software Defined Hardware. I was fortunate to participate the SDH program when I was a research scientist in Michael Taylor's group at University of Washington (2017 -- 2019), leading the hardware and low-level runtime group.
Software Define Hardware (SDH) is one of the DARPA Electronics Resurgence Initiative program, which aims to build runtime-reconfigurable hardware and software that enables near ASIC performance without sacrificing programmability for data-intensive algorithms.
University of Washington is one of the SDH performers to build Polymorphic hybrid ASIC/FPGA architectures based on the Celerity fabric.
A 7.3 M Output Non-Zeros/J, 11.7 M Output Non-Zeros/GB Reconfigurable Sparse Matrix–Matrix Multiplication Accelerator IEEE Journal of Solid-State Circuits 2020
A 7.3 M Output Non-Zeros/J Sparse Matrix-Matrix Multiplication Accelerator using Memory Reconfiguration in 40 nm In 2019 Symposium on VLSI Technology 2019