MaPU (Mathematical Processing Unit) is a novel architecture targeting data-intensive computing with great power efficiency and sustained computation throughput.

To achieve this goal, MaPU uses mathematical formulates style program model, directly mapped data path on CGRA fabric and groundbreaking memory system that supports simultaneous row-major and column major matrix with the same layout.

The Function Unit (FU) are connected via a cross bar to form a CGRA farbic


MaPU toolchain includes assembler/disassembler, compiler, simulator etc., for both scalar pipeline and micro-code pipeline. Complete source code can be found at

Tool name Based Open Source Framework
Compiler for State Machine based language Ragel &Bison & LLVM
C compiler for Scalar Pipeline Clang & LLVM
Assembler /Disassembler Ragel & Bison & LLVM
Linker Binutils Gold
Debugger for Scalar Pipeline GDB
Simulator ( Scalar & Microcode ) Gem5
Emulator OpenOCD

Prototype Chip

Left: Layout of a MaPU Core. Right: Packaged 40nm chip.

Chip Performance

Performance chart.


Please cite our HPCA’16 paper if you are inspired our work:

  title={MaPU: A novel mathematical computing architecture},
  author={Wang, Donglin and Xie, Shaolin and others},
  booktitle={2016 IEEE International Symposium on High Performance Computer Architecture (HPCA)},


  1. Parallel filtering method and corresponding apparatus Wang, Donglin, Yin, Leizu, Yang, Yongyong, Xie, Shaolin, and Wang, Tao 2018
  2. Methods and devices for multi-granularity parallel FFT butterfly computation Wang, Donglin, Wang, Tao, Xie, Shaolin, Hao, Jie, and Yin, Leizu 2016
  3. Data access method and device for parallel FFT computation Xie, Shaolin, Wang, Donglin, Lin, Xiao, Hao, Jie, Xue, Xiaojun, Wang, Tao, and Yin, Leizu 2016
  4. Parallel bit reversal devices and methods Xie, Shaolin, Wang, Donglin, Hao, Jie, Wang, Tao, and Yin, Leizu 2016
  5. Multi-granularity parallel storage system Wang, Donglin, Liu, Zijun, Xue, Xiaojun, Zhang, Xing, Zhang, Zhiwei, and Xie, Shaolin 2015
  6. Multi-granularity parallel storage system and storage Wang, Donglin, Xie, Shaolin, Xue, Xiaojun, Liu, Zijun, and Zhang, Zhiwei 2015